Panasonic's new substrate material improves package-level reliability by reducing warpage during packaging (mounting chips on the IC substrate followed by an encapsulation process). The coefficient of thermal expansion (CTE) of the new substrate material is much closer to that of silicon IC chips, reducing warpage caused by the thermal excursions during packaging processes.

During the reflow assembly process, when the semiconductor package is assembled onto the motherboard, the material lowers stress imparted to the solder balls - improving assembly-level reliability. The new material features excellent thickness tolerances, ensuring stable junctions between the substrate and the IC chips. This modified flexibility and buffering properties alleviate the stress on solder balls, improving the assembly-level reliability.

Features

• Low Thermal Expansion Coefficient (CTE) Close To That Of Silicon IC Chips Reduces Warping - Addressing A Critical Challenge With The IC Chip Packaging Process
• Retaining Low Thermal Expansion Properties Through A Stress Relaxation Technology Improves The Reliability Pf The Assembly Process
• Excellent Thickness Tolerances To Ensure Stable Junctions Between This Substrate And The IC Chips - Further Improving The Reliability Of The IC Package

Applications

Flip-Chip Ball Grid Array (FC-BGA) packages such as:

• Central Processing Unit (CPU)
• Graphics Processing Unit (GPU) 
• Field Programmable Gate Arrays (FPGA) 
• Application-Specific Integrated Circuit (ASIC)

The product is currently being presented at the 2021 IEEE 71st Electronic Components and Technology Conference (from June 1 to July 4, 2021).